1. Field of the Invention
The present invention relates in general to the field of electronic data storage devices and more particularly to a voltage bias generator for generating a voltage bias based on current comparisons.
2. Description of the Related Art
Electronic data storage devices, such as flash memories, are found in a wide array of electronic devices. The storage devices store data in memory cells. Memory cells generally store data as a digital signal. In a binary storage system, memory cells store data as a logical “1” or a logical “0”. A stable voltage bias reference allows accurate sensing of data content stored in the memory cells.
FIG. 1 depicts a conventional electronic data storage device 100 with a voltage bias generator 102. The voltage bias generator 102 generates a voltage bias Vref that serves as a reference voltage for sense amplifier 104. The electronic data storage device 100 also includes multiple memory cells 106 that store respective data in each memory cell. Sense amplifier 104 compares voltage bias Vref with the content of a memory cell to determine (“read”) the data stored by the memory cell. For example, if the content of the memory cell is greater than the voltage bias Vref, the memory cell stores a logical “1”. Otherwise, the memory cell stores a logical “0”. Thus, the voltage bias should be a known value to allow accurate reading of the memory cells.
To generate the voltage bias Vref, the voltage bias generator 102 includes a diode connected field effect transistor (FET) 108 to generate a constant voltage VGS. The value of VGS is determined by the drain current Iref and the physical properties of FET 108. A constant current source 110 generates drain current Iref. The FET 108 applies the voltage VGS to the non-inverting input terminal of an operational amplifier (OPAMP) 112. OPAMP 112 serves as a buffer, and the non-inverting input of OPAMP 112 provides a high output impedance to FET 108. To maintain a constant voltage bias Vref for sensing amplifier 104, OPAMP 112 is configured with unity feedback to the inverting terminal.
The voltage bias generator 102 works well in some applications. However, if the load has a significant reactive component and draws current, OPAMP 112 can exhibit performance impacting latency when charging the load to the voltage bias Vref. Additionally, OPAMP 112 includes an offset voltage Voffset. Thus, the voltage bias Vref does not equal VGS. The voltage bias Vref actually equals VGS−Voffset. Accurately predicting and replicating an exact value for the offset voltage Voffset is difficult and causes the sense amplifier 104 to have a wider margin between the voltage bias reference Vref and the data contents of the memory cells 106. Additionally, as components age and are affected by environmental and use characteristics, component values may drift. Drifting of component values can cause error in the reading of memory cells 106, or the error is compensated through additional error margins added to the voltage bias Vref and/or the sense amplifier 104.